HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 376
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bit 1: SPB0IO
0
1
Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port I/O data. Use the SPB0IO bit to
specify input or output of TxD pin. See the description of SPB0IO for details. SPB0DT bit is
output to the TxD pin when specified as output. The RxD pin value is read from the SPB0IO bit
regardless of the SPB0IO bit value. The initial value is undefined.
Bit 0 : SPB0DT
0
1
Block diagrams of the SCI I/O port pins are shown in figures 15.2 to 15.4 in section 15, I/O Ports.
13.2.9
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in the two channels.
356
Initial value:
The SCBRR setting is calculated as follows:
Asynchronous mode: N = [P /(64
Synchronous mode: N = [P /(8
B: Bit rate (bit/s)
N: SCBRR setting for baud rate generator (0
P : Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
Bit name:
Bit Rate Register (SCBRR)
see table 13.3.)
R/W:
Bit:
Description
The SPB0DT bit value is not output to the TxD pin.
The SPB0DT bit value is output to the TxD pin.
Description
I/O data level is low.
I/O data level is high.
R/W
7
1
R/W
6
1
2
R/W
2n – 1
2
5
1
2n – 1
B)]
B)]
R/W
4
1
10
N
10
6
255)
– 1
6
– 1
R/W
3
1
R/W
2
1
R/W
1
1
(Initial value)
(Initial value)
R/W
0
1
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