HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 259

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.3.4
DRAM Interface
DRAM Connection Method: When the memory type bits (DRAMTP2–DRAMTP0) in BCR1 are
set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM
space. The DRAM interface function can then be used to connect the SH7708 Series directly to
DRAM.
16 or 32 bits can be selected as the interface data width for area 3 when bits DRAMTP2 to
DRAMTP0 are set to 100, and 16 bits can be used for both area 2 and area when bits DRAMTP2
to DRAMTP0 are set to 101.
2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.
Signals used for connection when DRAM is connected to area 3 are RAS, CASHH, CASHL,
CASLH, CASLL, and RD/WR. CASHH and CASHL are not used when the data width is 16 bits.
When DRAM is connected to areas 2 and 3, the signals for area 2 DRAM connection are RAS2,
CAS2H, CAS2L, and RD/WR, and those for area 3 DRAM connection are RAS, CASLH,
CASLL, and RD/WR.
In addition to normal read and write access modes, high-speed page mode is supported for burst
access. Also, for DRAM connected to area 3, EDO mode, which enables the DRAM access time
to be increased by delaying the data sampling timing by 1/2 clock when reading, is supported in
addition to normal read and write access for burst mode.
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