HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 198

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

9.9
9.9.1
The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the
selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an
interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to
H'00 only by a power-on reset through the RESET pin. Use a word access to write to the WTCNT
counter, with H'5A in the upper byte. Use a byte access to read WTCNT.
9.9.2
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of
bits to select the clock used for the count, bits to select the timer mode, and overflow flags. Its
address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset
through the RESET pin. When a WDT overflow causes an internal reset, the WTCSR retains its
value. When used to count the clock settling time for canceling a standby, it retains its value after
counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper byte.
Use a byte access to read WTCSR.
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME
0
1
178
Initial value:
Initial value:
WDT Registers
Watchdog Timer Counter (WTCNT)
Watchdog Timer Control/Status Register (WTCSR)
R/W:
R/W:
Bit:
Bit:
TME
R/W
R/W
7
0
7
0
Description
Timer disabled: Count-up stops and WTCNT value is retained
Timer enabled
WT/IT
R/W
R/W
6
0
6
0
RSTS
R/W
R/W
5
0
5
0
WOVF
R/W
R/W
4
0
4
0
IOVF
R/W
R/W
3
0
3
0
CKS2
R/W
R/W
2
0
2
0
CKS1
R/W
R/W
1
0
1
0
(Initial value)
CKS0
R/W
R/W
0
0
0
0