HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 155

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

7.3.2
1. Making an instruction fetch/read/word setting made in the break bus cycle register
2. When instructions are fetched consecutively, 32 bits (two instructions) are fetched in one bus
3. With an instruction subject to a pre-execution break, the break is executed when it has been
4. With a post-execution condition, the instruction set as the break condition is executed and a
5. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
6. Instruction fetch cycle breaks cannot be specified consecutively for a delayed branch
(BBRA/BBRB) enables an instruction fetch cycle to be set as a break condition. In this case,
pre- or post-execution of the instruction can be selected by means of bit PCBA/PCBB in the
break control register (BRCR).
cycle. In this case, although only one bus cycle is generated, breaks can be set for both
instructions by setting the start addresses of the respective instructions in the break address
registers (BARA and BARB).
confirmed that the instruction has been fetched and is to be executed. Consequently, an
overrun-fetched instruction (an instruction fetched but not executed in the event of a branch or
exception) cannot be subject to a break. If an exception when an instruction subject to a break
is fetched, exception processing is performed first, and the break is executed only when the
instruction is re-executed.
Since a delayed branch instruction and delay slot instruction are executed as a single
instruction, if a pre-execution condition is specified for the delay slot instruction, a break is
made before execution of the delayed branch instruction. However, a pre-execution break
condition cannot be specified for an RTE instruction delay slot instruction.
break trap is generated before the next instruction is executed. In the same way, a break cannot
be specified for an overrun-fetch instruction. When a post-execution condition is set for a
delayed branch instruction, similarly, the break is made after executing the delay slot and
before executing the instruction at the branch destination.
Therefore, break data need not be set for an instruction fetch cycle break.
instruction and its delay slot.
Instruction Fetch Cycle Break
135