D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 141
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 4.4
4.5.2
Type
Power-on
reset
Manual
reset
UDI
reset
UDI Reset
TLB miss exception
PC and SR of the instruction that generated the exception are saved to SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0400.
To speed up TLB miss processing, the offset differs from other exceptions.
Conditions: UDI reset command input (see section 22.4.3, UDI Reset)
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details.
Conditions: Comparison of TLB addresses shows no address match.
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. If all ways are valid, 1 is added to
the RC bit in MMUCR. If there is one or more invalid way, they are set by priority starting
with way 0.
General Exceptions
Types of Reset
Conditions for Transition
to Reset State
RESETP = Low
RESETM = Low
UDI reset command input
CPU
Initialized
Initialized
Initialized
Rev. 5.00, 09/03, page 95 of 760
(See register configuration in
relevant sections)
On-Chip Peripheral Modules
Internal State
H'A0000000.
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