D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 388
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 388 of 809
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Bit 1—Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified
in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or
the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1. Even if the DE bit
is set to 1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
0
1
Bit 0—DMAC Enable Bit (DE): Enables operation of the corresponding channel.
Bit 0: DE
0
1
If an auto-request is specified (RS3 to RS0), transfer starts when this bit is set to 1. In an external
request or an internal module request, transfer starts when a transfer request is generated after this
bit is set to 1. Clearing this bit during transfer terminates the transfer.
Even if the DE bit is set, transfer is not enabled if the TE bit is 1, the DME bit in DMAOR is 0, or
the NMIF or AE bit in DMAOR is 1.
Rev. 5.00, 09/03, page 342 of 760
Description
Data transfers specified in DMATCR not completed
Clearing conditions: Writing 0 to TE after reading TE = 1
Data transfers specified in DMATCR completed
Description
Channel operation disabled
Channel operation enabled
Power-on reset, manual reset
(Initial value)
(Initial value)
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