D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 217
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3. When the condition is specified to be occurred after execution, the instruction set with the
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
7.3.3
1. The memory cycles in which CPU data access breaks occur are from instructions.
2. The relationship between the data access cycle address and the comparison condition for
Table 7.2
Access Size
Longword
Word
Byte
3. When the data value is included in the break conditions on B channel:
4. When the DMAC data access is included in the break condition:
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delay branch instruction, the break is generated at the
instruction that then first accepts the break.
There is thus no need to set break data for the break of the instruction fetch cycle.
operand size are listed in table 7.2:
This means that when address H'00001003 is set without specifying the size condition, for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data
values are included in break conditions, a break is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in two bytes at
bits 15–8 and bits 7–0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored.
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word or no specified operand
size. When the data value is included, select either byte or word.
Break by Data Access Cycle
Data Access Cycle Addresses and Operand Size Comparison Conditions
Address Compared
Compares break address register bits 31–2 to address bus bits 31–2
Compares break address register bits 31–1 to address bus bits 31–1
Compares break address register bits 31–0 to address bus bits 31–0
Rev. 5.00, 09/03, page 171 of 760
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