D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 149
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.1
5.1.1
The cache specifications are listed in table 5.1.
Table 5.1
5.1.2
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 256 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes 4). The data capacity per way is 4 kbytes (16 bytes
entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache
structure.
Parameter
Capacity
Structure
Locking
Line size
Number of entries
Write system
Replacement method
Overview
Features
Cache Structure
Cache Specifications
Specification
16 kbytes
Instruction/data mixed, 4-way set associative
Way 2 and way 3 are lockable
16 bytes
256 entries/way
P0, P1, P3, U0: Write-back/write-through selectable
Least-recently-used (LRU) algorithm
Section 5 Cache
Rev. 5.00, 09/03, page 103 of 760
256
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