D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 430
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.5.2
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with the address reload function on. Table 11.9
shows the transfer conditions and register settings.
Table 11.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Transfer Conditions
Transfer source: On-chip A/D converter
Transfer destination: Internal memory
Number of transfers: 128 (reloading 32 times)
Transfer source address: Incremented
Transfer destination address: Decremented
Transfer request source: A/D converter
Bus mode: Burst
Transfer unit: Longword
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
When the address reload function is on, the value set in SAR returns to the initially set value every
four transfers. In this example, when a transfer request is generated from the A/D converter, byte
data is read from the register at address H'04000080 in the A/D converter, and is written to
external memory address H'00400000. Since longword data has been transferred, the values in
SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus is kept and data transfers
are performed successively because this transfer is in burst mode.
After four transfers end, fifth and sixth transfers are performed if the address reload function is off,
and the value in SAR is incremented from H'0400008C to H'04000090, H'04000094
address reload function is on, DMA transfer stops after the fourth transfer ends, and the bus
request signal to the CPU is cleared. At this time, the value stored in SAR is not incremented
from H'0400008C to H'04000090, but returns to the initially set value, H'04000080. The value in
DAR continues to be decremented regardless of whether the address reload function is on or off.
Rev. 5.00, 09/03, page 384 of 760
Example of DMA Transfer between A/D Converter and External Memory
Converter and External Memory
Register
SAR2
DAR2
DMATCR2
CHCR2
DMAOR
Setting
H'04000080
H'00400000
H'00000080
H'00089E35
H'0101
If the
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