D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 180
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 180 of 809
- Download datasheet (5Mb)
Bit 12—I I I I R R R R L L L L S S S S Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the
IRQLVL bit is 1.
Bit 12: IRLSEN Description
0
1
Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to
the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
1
Bits 9 and 8—IRQ4 Sense Select (IRQ41S, IRQ40S): Select whether the interrupt signal to the
IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 9: IRQ41S
0
1
Bits 7 and 6—IRQ3 Sense Select (IRQ31S, IRQ30S): Select whether the interrupt signal to the
IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 7: IRQ31S
0
1
Rev. 5.00, 09/03, page 134 of 760
Pins IRLS3–IRLS0 disabled
Pins IRLS3–IRLS0 enabled
0
1
0
1
Bit 8: IRQ40S
0
1
0
1
Bit 6: IRQ30S
0
1
0
1
An interrupt request is detected at IRQ5 input falling edge
An interrupt request is detected at IRQ5 input rising edge
An interrupt request is detected at IRQ5 input low level
Reserved
Description
An interrupt request is detected at IRQ4 input falling edge
An interrupt request is detected at IRQ4 input rising edge
An interrupt request is detected at IRQ4 input low level
Reserved
Description
An interrupt request is detected at IRQ3 input falling edge
An interrupt request is detected at IRQ3 input rising edge
An interrupt request is detected at IRQ3 input low level
Reserved
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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