D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 553
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Switching Modes: When switching from receive mode to transmit mode, check that the receive
operation is completed before starting initialization, clearing RE to 0, and setting TE to 1. The
RDRF, PER, and ORER flags can be used to check if reception is completed. When switching
from transmit mode to receive mode, check that the transmit operation is completed before starting
initialization, clearing TE to 0, and setting RE to 1. The TEND flag can be used to check if
transmission is completed.
Interrupt Operation: In the smart card interface mode, there are three types of interrupts:
transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode,
the transmit-end interrupt (TEI) cannot be requested.
Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to
request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI
interrupt (table 15.9).
Table 15.9 Smart Card Mode Operating State and Interrupt Sources
Mode
Transmit mode
Receive mode
15.4
When the SCI is used as a smart card interface, be sure that all criteria in sections 15.4.1, Receive
Data Timing and Receive Margin in Asynchronous Mode and 15.4.2, Retransmission are applied.
15.4.1
In asynchronous mode, the SCI runs on a base clock with a frequency of 372 times the transfer
rate. During reception, the SCI samples the falling of the start bit using the base clock to achieve
internal synchronization. Receive data is latched internally at the rising edge of the 186th base
clock cycle (figure 15.8).
Usage Notes
Receive Data Timing and Receive Margin in Asynchronous Mode
State
Normal
Error
Normal
Error
Flag
TEND
FER/ERS
RDRF
PER,
ORER
Mask Bit
TIE
RIE
RIE
RIE
Rev. 5.00, 09/03, page 507 of 760
Interrupt Source
TXI
ERI
RXI
ERI
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