D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 482
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
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Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous
mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because
no stop bits are added.
When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit
setting is used only in asynchronous mode; it is ignored in synchronous mode. For the
multiprocessor communication function, see section 14.3.3, Multiprocessor Communication.
Bit 2: MP
0
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on-
chip baud rate generator. Four clock sources are available. P , P /4, P /16 and P /64 can be set
according to the setting of the CKS1 and CKS0 bits. For further information on the clock source,
bit rate register settings, and baud rate, see section 14.2.9, Bit Rate Register (SCBRR).
Bit 1: CKS1
0
1
Note: P : Peripheral clock
Rev. 5.00, 09/03, page 436 of 760
2. When transmitting, two 1-bits are added at the end of each transmitted character.
Description
One stop bit *
Two stop bits *
Description
Multiprocessor function disabled
Multiprocessor format selected
Bit 0: CKS0
0
1
0
1
1
2
Description
P
P /4
P /16
P /64
(Initial value)
(Initial value)
(Initial value)
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