D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 435
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 435 of 809
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12.1
The SH7709S has a three-channel (channels 0 to 2) 32-bit timer unit (TMU).
12.1.1
The TMU has the following features:
Each channel is provided with an auto-reload 32-bit down counter.
Channel 2 is provided with an input capture function.
All channels are provided with 32-bit constant registers and 32-bit down counters that can be
read or written to at any time.
All channels generate interrupt requests when the 32-bit down counter underflows
(H'00000000
Allows selection between 6 counter input clocks: External clock (TCLK), on-chip RTC output
clock (16 kHz), P /4, P /16, P /64, P /256. (P is the internal clock for peripheral modules.)
See section 9, On-Chip Oscillation Circuits, for more information on the clock pulse generator.
All channels can operate when the SH7709S is in standby mode: When the RTC output clock
is being used as the counter input clock, the SH7709S is still able to count in standby mode.
Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral
module used has an internal bus width of 16 bits, a time lag can occur between the time when
the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read
value caused by this time lag, a synchronization circuit is built into the TCNT so that the entire
32-bit data in the TCNT can be read at once.
The maximum operating frequency of the 32-bit counter is 2 MHz on all channels: Operate the
SH7709S so that the clock input to the timer counters of each channel (obtained by dividing
the external clock and internal clock with the prescaler) does not exceed the maximum
operating frequency.
Overview
Features
H'FFFFFFFF).
Section 12 Timer (TMU)
Rev. 5.00, 09/03, page 389 of 760
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