D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 254
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to the chip. In modes 0 to 2, the system clock is generated from the
output of the chip’s CKIO pin. Consequently, if a large number of ICs are operating on the clock
cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale
system. If a large number of ICs are operating on the clock cycle, a clock generator with a number
of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Table 9.4
Clock
Mode FRQCR PLL1
0
Rev. 5.00, 09/03, page 208 of 760
H'0100
H'0101
H'0102
H'0111
H'0112
H'0115
H'0116
H'0122
H'0126
H'012A
H'A100
H'A101
H'E100
H'E101
H'A111
Available Combinations of Clock Mode and FRQCR Values
ON ( 1) ON ( 1) 1:1:1
ON ( 1) ON ( 1) 1:1:1/2
ON ( 1) ON ( 1) 1:1:1/4
ON ( 2) ON ( 1) 2:1:1
ON ( 2) ON ( 1) 2:1:1/2
ON ( 2) ON ( 1) 1:1:1
ON ( 2) ON ( 1) 1:1:1/2
ON ( 4) ON ( 1) 4:1:1
ON ( 4) ON ( 1) 2:1:1
ON ( 4) ON ( 1) 1:1:1
ON ( 3) ON ( 1) 3:1:1
ON ( 3) ON ( 1) 3:1:1/2
ON ( 3) ON ( 1) 1:1:1
ON ( 3) ON ( 1) 1:1:1/2
ON ( 6) ON ( 1) 6:1:1
PLL2
Clock Rate *
(I:B:P)
Input Frequency
Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
CKIO Frequency
Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
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