D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 640
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.5.2
Note: * Undefined
The port D data register (PDDR) is a 6-bit readable/writable and 2-bit read-only register that stores
data for pins PTD7 to PTD0. Bits PD7DT to PD0DT correspond to pins PTD7 to PTD0. When the
pin function is general output port, if the port is read, the value of the corresponding PDDR bit is
returned directly. When the function is general input port, if the port is read, the corresponding pin
level is read. Table 19.8 shows the function of PDDR.
PDDR is initialized to B'0*0*0000 by a power-on reset. After initialization, the general input port
function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are
read from bits PD7DT—PD3DT, PD1DT, and PD0DT. PDDR retains its previous value in
standby mode and sleep mode, and in a manual reset.
Note that the low level is read if bits 6 and 4 are read except in general-purpose input.
Table 19.8 Port D Data Register (PDDR) Read/Write Operations
PDnMD1
0
1
PDnMD1
0
1
Rev. 5.00, 09/03, page 594 of 760
Initial value:
Port D Data Register (PDDR)
PDnMD0
0
1
0
1
PDnMD0
0
1
0
1
R/W:
Bit:
PD7DT
R/W
7
0
Pin State
Other function
(see table 18.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Pin State
Other function
(see table 18.1)
Reserved
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PD6DT
R
6
*
PD5DT
R/W
Read
PDDR value
PDDR value
Pin state
Pin state
Read
Low level
Low level
Pin state
Pin state
5
0
PD4DT
R
4
*
Write
Value is written to PDDR, but does not
affect pin state
Write value is output from pin
Value is written to PDDR, but does not
affect pin state
Value is written to PDDR, but does not
affect pin state
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
PD3DT
R/W
3
0
PD2DT
R/W
2
0
(n = 0, 1, 2, 3, 5, 7)
PD1DT
R/W
1
0
(n = 4, 6)
PD0DT
R/W
0
0
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