D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 218
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.3.4
1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break
2. In sequential break specification, a logical bus or internal bus can be selected and the execution
7.3.5
The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows
depending on the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
2. When instruction fetch (after instruction execution) is specified as a break condition:
3. When data access (address only) is specified as a break condition:
4. When data access (address + data) is specified as a break condition:
Rev. 5.00, 09/03, page 172 of 760
condition matches after channel A break condition matches. A user break is ignored even if
channel B break condition matches before channel A break condition matches. When channels
A and B condition match at the same time, the sequential break is not issued.
times break condition can be also specified. For example, when the execution times break
condition is specified, the break condition is satisfied at channel B condition match with BETR
= H'0001 after channel A condition match.
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
The PC value saved is the address of the instruction to be executed following the instruction in
which the break condition matches. The fetched instruction is executed, and a break occurs
before the execution of the next instruction.
The PC value is the address of the instruction to be executed following the instruction that
matched the break condition. The instruction that matched the condition is executed and the
break occurs before the next instruction is executed.
The PC value is the start address of the instruction that follows the instruction already executed
when break processing started up. When a data value is added to the break conditions, the
place where the break will occur cannot be specified exactly. The break will occur before the
execution of an instruction fetched around the data access where the break occurred.
Sequential Break
Value of Saved Program Counter
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