D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 223
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6. Register specifications
Break Condition Specified to a CPU Data Access Cycle
1. Register specifications
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
A user break occurs after an instruction with ASID = H'80 and address H'00008000 to
H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010
to H'00008016 are executed.
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, a user break occurs with ASID = H'80 during longword read to address
H'00123454, word read to address H'00123456, or byte read to address H'00123456. On
channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses
H'000ABC00 to H'000ABCFE.
Address:
Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not
Address:
Data:
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
Address:
Bus cycle: CPU/data access/read (operand size is not included in the condition)
Address:
Data:
Bus cycle: CPU/data access/write/word
Channel A
Channel B
Channel A
Channel B
H'00008404, Address mask: H'00000FFF, ASID: H'80
included in the condition)
H'00008010, Address mask: H'00000006, ASID: H'70
H'00000000, Data mask: H'00000000
included in the condition)
H'00123456, Address mask: H'00000000
H'000ABCDE, Address mask: H'000000FF, ASID: H'70
H'0000A512, Data mask: H'00000000
Rev. 5.00, 09/03, page 177 of 760
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