D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 227

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 3⎯Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
0
1
Bits 2 to 0⎯Data Transfer Select (DTS2 to DTS0): These bits select the data transfer activation
source. Some of the selectable sources differ between channels A and B.*
Note: * See section 7.3.4, Data Transfer Control Registers (DTCR).
Bit 2
DTS2
0
1
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 7.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Bit 1
DTS1
0
1
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
Bit 0
DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from 16-bit timer channel 0
Compare match/input capture A interrupt from 16-bit timer channel 1
Compare match/input capture A interrupt from 16-bit timer channel 2
Conversion-end interrupt from A/D converter
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
Rev.5.00 Sep. 12, 2007 Page 197 of 764
7. DMA Controller
REJ09B0396-0500
(Initial value)
(Initial value)