D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 366

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9. 16-Bit Timer
9.5.2
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 9.36 shows the timing.
9.5.3
Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare
match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources
of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag
are set to 1.
The priority order of the channels can be modified in interrupt priority register A (IPRA). For
details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 2 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 9.6 lists the interrupt sources.
Rev.5.00 Sep. 12, 2007 Page 336 of 764
REJ09B0396-0500
φ
Address
IMF, OVF
Timing of Clearing of Status Flags
Interrupt Sources and DMA Controller Activation
Figure 9.36 Timing of Clearing of Status Flags
T
1
TISR write cycle
TISR address
T
2
T
3