D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 524
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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14. Smart Card Interface
14.2.3
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit
Initial value
Read/Write
Bit 7⎯GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
Bit 7
GM
0
1
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5,
Serial Mode Register (SMR).
14.2.4
The function of SCR bits 1 and 0 is modified in smart card interface mode.
Bit
Initial value
Read/Write
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6,
Serial Control Register (SCR).
Rev.5.00 Sep. 12, 2007 Page 494 of 764
REJ09B0396-0500
Serial Mode Register (SMR)
Serial Control Register (SCR)
Description
Normal smart card interface mode operation
•
•
GSM mode smart card interface mode operation
•
•
R/W
The TEND flag is set 12.5 etu after the beginning of the start bit.
Clock output on/off control only.
The TEND flag is set 11.0 etu after the beginning of the start bit.
Clock output on/off and fixed-high/fixed-low control.
R/W
GM
TIE
7
0
7
0
CHR
R/W
R/W
RIE
6
0
6
0
R/W
R/W
PE
TE
5
0
5
0
R/W
R/W
O/E
RE
4
0
4
0
STOP
MPIE
R/W
R/W
3
0
3
0
TEIE
R/W
R/W
MP
2
0
2
0
CKS1
CKE1
R/W
R/W
1
0
1
0
(Initial value)
CKS0
CKE0
R/W
R/W
0
0
0
0
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