D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 529

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
2. Indirect Convention (SDIR = SINV = O/E = 1)
14.3.5
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
With the indirect convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3067 Group, inversion specified by the SINV bit applies only to the data bits, D7 to
D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies
to both transmission and reception.
(Z)
(Z)
B =
Clock
Ds
Ds
A
A
1488 × 2
D0
D7
Z
Z
2n–1
D1
D6
Z
Z
φ
× (N + 1)
D2
D5
A
A
D3
D4
A
Z
× 10
D4
D3
6
Z
A
D5
D2
A
Z
D6
D1
A
A
Rev.5.00 Sep. 12, 2007 Page 499 of 764
D7
D0
A
A
Dp
Dp
Z
Z
14. Smart Card Interface
(Z)
(Z)
State
State
REJ09B0396-0500