D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 405

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Compare Match Count Mode
• Channels 0 and 1:
• Channels 2 and 3:
Caution: Do not set 16-bit count mode and compare match count mode simultaneously within the
same group, as the 8TCNT input clock will not be generated and the counters will not operate.
10.4.6
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO
can be selected. In 16-bit count mode, 16-bit input capture can be used.
Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)
• Channel 1:
• Channel 3:
⎯ OVF Flag Operation
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
Channels 0 and 1 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
Channels 2 and 3 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
⎯ Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
⎯ Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
signal (TMIO
signal (TMIO
Input Capture Setting
overflows (from H'FFFF to H'0000).
H'FF to H'00).
1
3
) with bits OIS3 and OIS2 in 8TCSR1.
) with bits OIS3 and OIS2 in 8TCSR3.
1
or TMIO
3
). Rising edge, falling edge, or both edge detection
Rev.5.00 Sep. 12, 2007 Page 375 of 764
REJ09B0396-0500
10. 8-Bit Timers