D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 453

MCU 3V 0K 100-TQFP

D13007VX13V

Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13007VX13V

Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
12.3.4
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but
the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
12.4
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
φ
TCNT
Overflow signal
OVF
WDT internal
reset
WRST
Timing of Setting of Watchdog Timer Reset Bit (WRST)
Interrupts
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
H'FF
H'00
Rev.5.00 Sep. 12, 2007 Page 423 of 764
12. Watchdog Timer
REJ09B0396-0500

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