HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 109

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

4.4
4.4.1
The reset sequence is used to power up or restart the SH7708 Series from the initialization state.
The RESET signal is sampled every clock cycle, and in the case of a power-on reset, all
processing being executed (excluding the RTC) is suspended, all unfinished events are canceled,
and reset processing is executed immediately. In the case of a manual reset, however, processing
to retain external memory contents is continued. The BREQ (bus request) signal is used to
distinguish between a power-on reset (high-level input) and manual reset (low-level input). The
reset sequence consists of the following operations:
4.4.2
An interrupt processing request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
4.4.3
When the SH7708 Series encounters any exception condition other than a reset or interrupt
request, it executes the following operations:
The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode.
The BL bit in SR is set to 1, masking any subsequent exceptions.
The RB bit in SR is set to 1.
An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11–
0 of the EXPEVT register to identify the exception event.
Instruction execution jumps to the user-written exception handler at address H'A0000000.
The contents of the PC and SR are saved in SPC and SSR, respectively.
The BL bit in SR is set to 1, masking any subsequent exceptions.
The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode.
The RB bit in SR is set to 1.
An encoded value identifying the exception event is written to bits 11–0 of the INTEVT
register.
Instruction execution jumps to the vector location designated by the sum of the value of the
contents of the vector base register (VBR) and H'00000600 to invoke the exception handler.
The contents of the PC and SR are saved in the SPC and SSR, respectively.
The BL bit in SR is set to 1, masking any subsequent exceptions.
The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode.
Exception Handler Operation
Reset
Interrupts
General Exceptions
89