HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 211

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 10.1 Pin Configuration (Preliminary) (cont)
Pin Name
Data enable 0
Data enable 1
Data enable 2
Data enable 3
Read
Wait
16-bit I/O
Clock enable
Bus release
request
Bus release
acknowledgment
Area 0 bus width,
PCMCIA card
select
Endian switching/
low address strobe
Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A5PCM. Output is selected
2. MD4/CE2B input/output switching is performed by BCR1.A6PCM. Output is selected
3. MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected
when BCR1.A5PCM = 1.
when BCR1.A6PCM = 1.
when BCR1.DRAMTP (2–0) = 101.
Signal
DQMLL/WE0
DQMLU/WE1
DQMUL/WE2/
ICIORD
DQMUU/WE3/
ICIOWR
RD
WAIT
IOIS16
CKE
BREQ
BACK
MD3/CE2A*
MD4/CE2B*
MD5/RAS2*
1
2
3
,
I/O
O
O
O
O
O
I
I
O
I
O
I/O
I/O
Description
When synchronous DRAM is used, selects D7–D0.
For other memory, D7–D0 write strobe signal.
When synchronous DRAM is used, selects D15–D8.
When PCMCIA is used, strobe signal that indicates
the write cycle. For other memory, D15–D8 write
strobe signal.
When synchronous DRAM is used, selects D23–
D16. For other memory, D23–D16 write strobe
signal. For PCMCIA, strobe signal indicating I/O
read.
When synchronous DRAM is used, selects D31–
D24. For other memory, D31–D24 write strobe
signal. For PCMCIA, strobe signal indicating I/O
write.
Strobe signal indicating read cycle
Wait state request signal (synchronous signal)
Signal indicating PCMCIA 16-bit I/O. Valid only in
little-endian mode. (Fix low in big-endian mode.)
Connected to clock enable control signal of
synchronous DRAM
Bus release request signal
Bus release acknowledge signal
Signal controlling bus width of physical space area
0. When PCMCIA is used, CE2A and CE2B.
Signal setting endian for all spaces on reset. When
area 2 DRAM is connected, area 2 DRAM RAS
signal
191