HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 409

IC SUPERH MPU ROMLESS 144LQFP

HD6417708RF100A

Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708RF100A

Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for
receiving serial data. When switching from asynchronous mode to synchronous mode, make sure
that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set
and both transmitting and receiving will be disabled.
The procedure for receiving serial data is:
1. Receive error handling and break detection: If a receive error occurs, read the ORER bit in
2. SCI status check and receive data read: Read the serial status register (SCSSR), check that
3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the MSB (bit 7)
SCSSR to identify the error. After executing the necessary error handling, clear ORER to 0.
Transmitting/receiving cannot resume if ORER remains set to 1.
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
of the current frame is received.
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