HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 299
![IC SUPERH MPU ROMLESS 144LQFP](/photos/28/61/286126/144-lqfp__plqp0144kb-a_sml.jpg)
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708RF100A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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With pseudo-SRAM, self-refresh mode is entered by holding the RFSH signal low for at least the
prescribed time. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1.
The self-refresh state is maintained while the CKE signal is low. Pseudo-SRAM cannot be
accessed while in self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0.
After self-refresh mode has been cleared, access to pseudo-SRAM is disabled for the number of
cycles specified by the TPC bits in MCR, but if the refresh reset time needed to return from self-
refreshing is longer than this interval, coding must be provided to ensure that no access—
including auto-refresh—is made to pseudo-SRAM. Self-refresh timing is shown in figure 10.38.
Settings must be made so that self-refresh clearing and data retention is performed correctly after
self-refresh mode is cleared, and auto-refreshing is performed at the correct intervals. If the
transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time
should be taken into consideration when setting the initial value of RTCNT.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual
reset.
Power-On Sequence: After powering pseudo-SRAM on, a minimum wait time of 100 µs is
requested during which no access can be performed, followed by the prescribed number (usually 8
or more) of dummy auto-refresh cycles. As the bus state controller does not perform any special
operations for a power-on reset, the power-on sequence must be carried out by the initialization
program executed after a power-on reset.
CKIO
OE/RFSH
CE
TRc
Figure 10.38 Pseudo-SRAM Self-Refreshing
(High)
TRr1
TSR
TSR2
(Tpc)
(Tpc)
279
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