HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 152
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Quantity
Price
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HD6417708RF100AV
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7.2.11
The break control register (BRCR) is a 16-bit read/write register that controls user breaks.
BRCR:
1. Determines whether to use channels A and B as two independent channels or as sequential
2. Selects whether to break before or after instruction execution during the instruction fetch cycle.
3. Determines whether to include the BDRB register in the channel B comparison conditions.
It also has a condition-match flag. A power-on or manual reset initializes BRCR to H'0000.
Bit 15—Condition Match Flag A (CMFA): Set to 1 when the break conditions set in channel A are
met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 15: CMFA
0
1
Bit 14—Condition Match Flag B (CMFB): Set to 1 when the break conditions set in channel B are
met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 14: CMFB
0
1
Bits 13 to 11—Reserved: These bits always read 0. The write value should always be 0.
132
conditions.
Initial value:
Initial value:
Bit name:
Bit name:
Break Control Register (BRCR)
R/W:
R/W:
Bit:
Bit:
CMFA
DBEB
R/W
R/W
15
0
7
0
Description
Channel A break conditions do not match.
Channel A break conditions match.
Description
Channel B break conditions do not match.
Channel B break conditions match.
CMFB
PCBB
R/W
R/W
14
0
6
0
13
—
—
0
R
5
0
R
12
—
—
0
R
4
0
R
SEQ
R/W
11
—
0
R
3
0
PCBA
R/W
10
—
0
2
0
R
—
—
9
0
R
1
0
R
(Initial value)
(Initial value)
—
—
8
0
R
0
0
R
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