HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 97

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.6
In order for TLB operations to be managed by software, TLB contents can be read or written to in
privileged mode using the MOV instruction. The TLB is assigned to the P4 area in virtual address
space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000–H'F2FFFFFF,
and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000–H'F3FFFFFF. The V bit in
the address array can also be accessed from the data array. Only longword access is possible for
both the address array and the data array.
3.6.1
The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the
32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 3.14 (1)).
In the address field, specify the entry address for selecting the entry (bits 16–12), W for selecting
the way (bits 9–8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3) and H'F2 to indicate address
array access (bits 31–24). The IX bit in MMUCR indicates whether an EX-OR is taken of the
entry address and ASID.
When writing, specify bit 7 as the A bit. The A bit indicates whether addresses are compared
during writing. When the A bit is 1, the VPNs of the four entries selected by the entry addresses
are compared to the VPN to be written into the address array specified in the data field. Writing
takes place to the way that has a hit. When a miss occurs, nothing is written to the address array
and no operation occurs. The way number specified in bits 9–8 is not used. The item compared is
determined by the SZ and SH bits of the entry selected by the entry address, the SV bit in
MMUCR and the MD bit in SR, just as in ordinary operations (see section 3.3.3).
When the A bit is 0, it is written to the entry selected with the entry address and way number
without comparing addresses.
When reading, the VPN (31–17, 11–10), V bit, and ASID of the entry specified by the entry
address and way number are read in the format of the data field in figure 3.14 without comparing
addresses. Zero is read in the data field (16–12).
To invalidate a specific entry, specify the entry and write 0 to its V bit. When 1 is specified for the
A bit, only the required VPN entry is invalidated.
Memory-Mapped TLB
Address Array
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