HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 427
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Company:
Part Number:
HD6417708RF100A
Manufacturer:
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Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
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Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
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Quantity:
20 000
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The operating sequence is:
1. The data line is high impedance when not in use and is fixed high with a pull-up resistor.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
3. On the smart card interface, the data line returns to high impedance after this. The data line is
4. The receiving side checks parity. When the data is received normally with no parity errors, the
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it
14.3.4
Table 14.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or
0 must be set to the indicated value. The settings for the other bits are described below.
Table 14.3 Register Settings for the Smart Card Interface
Register
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
SCRDR
SCSCMR
Note: Dashes indicate unused bits.
bit (Ds, low level). The start bit is followed by eight data bits (D0–D7) and a parity bit (Dp).
pulled high with a pull-up resistor.
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up resistor.
does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
Register Settings
Address
H'FFFFFE80
H'FFFFFE82
H'FFFFFE84
H'FFFFFE86
H'FFFFFE88
H'FFFFFE8A
H'FFFFFE8C
Bit 7
C/A
BRR7
TIE
TDR7
TDRE
RDR7
—
Bit 6
0
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
FER/
ERS
RDR4
—
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1
TDR1
0
RDR1
—
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
407
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