HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 162
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
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Table 8.1
Mode
Sleep
mode
Standby
mode
Hardware
standby
mode
Module
standby
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock
8.1.2
Table 8.2 shows the configuration of the control register for the power-down modes.
Table 8.2
Name
Standby control register
Note: * Initialized by a power-on reset. In a manual reset, the register contents are retained.
142
2. Depends on the on-chip supporting module.
3. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock
Register Configuration
Transition
Conditions
Execute SLEEP
instruction with
STBY bit cleared
to 0 in STBCR
Execute SLEEP
instruction with
STBY bit set to 1
in STBCR
Drive CA pin
low
Set MSTP bit of
STBCR to 1
TMU external pin: Held
SCI external pin: Reset
(RTC)). TMU still runs when output of the RTC is used as input to its counter (see
section 11, Timer (TMU)).
(RTC)). The TMU does not run.
Power-Down Modes
Register Configuration
Abbreviation
STBCR
State
CPG CPU
Runs Halts
Halts Halts
Halts Halts
Runs Runs Held Held
(Reg-
ister
held)
(Reg-
ister
held)
(Reg-
ister
held)
CPU
Reg-
ister
Held Held
Held Held
Held Held
R/W
R/W
On-Chip
Memory
Initial Value
H'00*
On-Chip
Peripheral
Modules
Run
Halts*
Halts*
Specified
module
halts
1
3
Address
H'FFFFFF82
Pins
Held Refresh
Held Self-
Held Self-
*
2
External
Memory
refresh
refresh
Refresh
Access Size
Byte
Canceling
Procedure
1. Interrupt
2. Reset
1. Interrupt
2. Reset
Power-on
reset
1. Clear
2. Reset
MSTP
bit to 0
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