HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 207

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.1
The bus state controller (BSC) divides physical address space and outputs control signals for
various types of memory and bus interface specifications. BSC functions enable the SH7708
Series to link directly with DRAM, synchronous DRAM, pseudo-SRAM, SRAM, ROM, and other
memory storage devices without an external circuit. The BSC also allows direct connection to
PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a
compact system.
10.1.1
The BSC has the following features:
Physical address space is divided into seven areas
Direct interface to DRAM
Direct interface to synchronous DRAM
A maximum 64 Mbytes for each of the seven areas, 0–6
Area bus width can be selected by register (area 0 is set by external pin)
Wait states can be inserted using the WAIT pin
Wait state insertion can be controlled through software. Register settings can be used to
The type of memory connected can be specified for each area, and control signals are
Wait cycles are automatically inserted to avoid data bus conflict for continuous memory
Multiplexes row/column addresses according to DRAM capacity
Supports burst operation (high-speed page mode, hyper page mode)
Supports CAS-before-RAS refresh and self-refresh
Performs low power 4-CAS-system byte control
Multiplexes row/column addresses according to synchronous DRAM capacity
Supports burst operation
Has both auto-refresh and self-refresh functions
specify the insertion of 1–10 cycles independently for each area (areas 1 and 2 have a
common setting)
output for direct memory connection
accesses to different areas or writes directly following reads of the same area
Controls timing of DRAM direct-connection control signals according to register settings
Controls timing of synchronous DRAM direct-connection control signals according to
register setting
Overview
Features
Section 10 Bus State Controller (BSC)
187