HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 311
![IC SUPERH MPU ROMLESS 144LQFP](/photos/28/61/286126/144-lqfp__plqp0144kb-a_sml.jpg)
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708RF100A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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I/O Card Interface Timing: Figures 10.47 and 10.48 show the timing for the PCMCIA I/O card
interface.
The I/O card interface is supported only for physical space area 6. Switching between the I/O card
interface and the IC memory card interface is performed according to the accessed address. When
PCMCIA is designated for physical space area 6, the bus access is automatically performed as an
I/O card interface access when a physical address from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a noncacheable area in
virtual space (P2 or P3 space) or an area specified as noncacheable by the MMU.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for
area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as
being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle
being executed, followed automatically by a data access for the remaining 8 bits.
Figure 10.49 shows the basic timing for dynamic bus sizing.
In big-endian mode, the IOIS16 signal is not supported.
In big-endian mode, the IOIS16 signal should be fixed low.
291
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