HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 337
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
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11.4.2
The status flag can be cleared by writing a 0 from the CPU. Figure 11.9 shows the timing.
11.4.3
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception
source register (INTEVT) for these interrupts and interrupt handling occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 6,
Interrupt Controller) and section 4, Exception Handling. Table 11.3 lists TMU interrupt sources.
Table 11.3 TMU Interrupt Sources
Channel
0
1
2
2
Peripheral address bus
Status Flag Clear Timing
Interrupt Sources and Priorities
UNF, ICPF
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
P
Figure 11.9 Status Flag Clear Timing
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
T1
TCR write cycle
T2
TCR address
T3
Priority
High
Low
317
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