HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 45

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 2.2
Addressing
Mode
PC-relative
Immediate
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (x1, x2, or x4) is performed according to the
operand size. This is done to clarify the operation of the IC. Refer to the relevant assembler
notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12; PC-relative
Addressing Modes and Effective Addresses (cont)
Instruction
Format
Rn
#imm:8
#imm:8
#imm:8
Effective Address Calculation Method
Effective address is sum of register PC and
Rn contents.
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA
instruction is zero-extended and multiplied
by 4.
PC
Rn
+
PC + Rn
Calculation Formula
PC + Rn
—
—
—
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