HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 136
![IC SUPERH MPU ROMLESS 144LQFP](/photos/28/61/286126/144-lqfp__plqp0144kb-a_sml.jpg)
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708RF100A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708RF100A
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417708RF100AV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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6.3.2
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin
NMI and indicates the input signal level to the NMI pin. This register is initialized by a power-on
reset or manual reset. It is not initialized in standby mode.
Note: When NMI input is high: 1; when NMI input is low: 0.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. It cannot be modified.
Bit 15: NMIL
0
1
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
0
1
Bits 14–9 and 7–0—Reserved: These bits always read 0. The write value should always be 0.
116
Initial value:
Initial value:
Bit name:
Bit name:
Interrupt Control Register (ICR)
R/W:
R/W:
Bit:
Bit:
NMIL
0/1*
15
—
R
7
0
R
Description
NMI input level is low
NMI input level is high
Description
Interrupt request is detected on the falling edge of NMI input
(Initial value)
Interrupt request is detected on rising edge of NMI input
14
—
—
0
R
6
0
R
13
—
—
0
R
5
0
R
12
—
—
0
R
4
0
R
11
—
—
0
R
3
0
R
10
—
—
0
R
2
0
R
—
—
9
0
R
1
0
R
NMIE
R/W
—
8
0
0
0
R
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