HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 119
HD6417708RF100A
Manufacturer Part Number
HD6417708RF100A
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708RF100A
Core Processor
SH-2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3.15 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
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In RAM mode, two ways are used as cache (way 0 and way 1). Bit 5 of the LRU bits indicates
which way is to be replaced. When bit 5 is 0, way 1 is to be replaced. When bit 5 is 1, way 0 is to
be replaced.
The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
Table 5.2
LRU (5–0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
5.1.3
Table 5.3 shows details of the cache control register.
Table 5.3
Register
Cache control register
Note: * Initialized by a power-on reset or manual reset.
5.2
5.2.1
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has an RA bit (which switches the cache operation mode between RAM mode and normal mode),
a CF bit (which invalidates all cache entries), a WT bit and a CB bit* (which selects either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached. When updating the contents of the CCR register,
always set bit 4 to 0. Figure 5.2 shows the configuration of the CCR register. CB bit is not
supported in emulator.
Note: * SH7708S, SH7708R Only
Register Configuration
Register Description
Cache Control Register (CCR)
LRU and Way Replacement in Normal Mode
Register Configuration
Abbr.
CCR
R/W
R/W
Size
Longword
Way to be Replaced
3
2
1
0
Initial Value*
H'00000000
Address
H'FFFFFFEC
99
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