HD64F2166VTE33 Renesas Electronics America, HD64F2166VTE33 Datasheet - Page 450

• Manufacturer Part Number: HD64F2166VTE33
• Description: IC H8S MCU FLASH 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2166VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 14.26. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 14.27. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
Rev. 3.00, 03/04, page 408 of 830
In normal transmission/reception
When a parity error is generated
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Figure 14.25 Data Formats in Normal Smart Card Interface Mode
(Z)
(Z)
Start bit
Parity bit
Error signal
Figure 14.27 Inverse Convention (SDIR = SINV = O/E = 1)
Ds
Ds
Figure 14.26 Direct Convention (SDIR = SINV = O/E = 0)
Ds
Ds
A
A
D0
D0
D7
D0
Z
Z
D1
D1
D6
D1
Z
Z
Output from the transmitting station
Output from the transmitting station
D2
D2
D5
D2
A
A
D4
D3
D3
D3
A
Z
D3
D4
A
Z
D4
D4
D2
D5
A
Z
D5
D5
D1
D6
A
A
D6
D6
D0
D7
A
A
Dp
Dp
D7
D7
Z
Z
Dp
Dp
(Z) state
(Z) state
Output from
the receiving station
DE