HD64F2166VTE33 Renesas Electronics America, HD64F2166VTE33 Datasheet - Page 60

• Manufacturer Part Number: HD64F2166VTE33
• Description: IC H8S MCU FLASH 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2166VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.2
The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a
maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address
space. The mode is selected by the LSI's mode pins.
Note: * Not available in this LSI.
2.2.1
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
• Extended registers (En)
• Instruction set
• Exception vector table and memory indirect branch addresses
• Stack structure
Note: Normal mode is not available in this LSI.
Rev. 3.00, 03/04, page 18 of 830
Linear access to a maximum address space of 64 kbytes is possible.
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-
increment (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
CPU Operating Modes
Normal Mode