HD64F2166VTE33 Renesas Electronics America, HD64F2166VTE33 Datasheet - Page 765

• Manufacturer Part Number: HD64F2166VTE33
• Description: IC H8S MCU FLASH 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2166VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 22.2 Crystal Resonator Parameters
Frequency(MHz)
R
C
22.1.2
Figure 22.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin
open, incidental capacitance should be 10 pF or less.
To input an inverted clock to the XTAL pin, the external clock should be set to high in standby
mode, subactive mode, subsleep mode, and watch mode. The frequency of the external clock
should be the same as that of the system clock (φ) when PFSEL is high. When PFSEL is low, an
external clock of 1/4 times the frequency of the system clock (φ) should be used.
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t
signal output is not determined during the t
in reset state. For the external clock output stabilization delay time, refer to table 25.5 and figure
25.8.
S
0
(max) (pF)
(max) (Ω)
External Clock Input Method
(b) Example of external clock input when an inverted clock is input to XTAL pin
Figure 22.4 Example of External Clock Input
EXTAL
XTAL
EXTAL
XTAL
5
100
7
(a) Example of external clock input when XTAL pin left open
8
80
7
DEXT
10
70
7
cycle, a reset signal should be set to low to hold it
Open
12
60
7
External clock input
External clock input
Rev. 3.00, 03/04, page 723 of 830
16
50
7
DEXT
) has passed. As the clock
20
40
7
25
30
7