D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 1034

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.3.8
OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or
continues data transfer.
Rev. 2.00 Feb. 12, 2010 Page 950 of 1330
REJ09B0554-0200
Bit
7
6
5
Bit
Name
CMDOFF
—
RD_
CONTI
Operation Control Register (OPCR)
Initial
Value
0
0
0
Initial value:
R/W:
Bit:
R/W
R/W
R
R/W
CMD
OFF
R/W
7
0
Description
Command Off
Aborts all command operations (MMCIF command
sequence) when 1 is written after a command is
transmitted. This bit is then cleared automatically.
Write enabled period: From command transmission
completion to command sequence end
Write of 0: Operation is not affected.
Write of 1: Command sequence is forcibly aborted.*
* The transfer clock output resumes if the transfer clock
Reserved
This bit is always read as 0. The write value should always
be 0.
Read Continue
Transfer clock output and read data reception are resumed
when 1 is written while the transfer clock has been halted
by FIFO full or termination of block reading in multiblock
read.
This bit is cleared automatically when 1 is written and
reading is resumed
Write enabled period: While MCCLK for read data
reception is halted
Write of 0: Operation is not affected.
Write of 1: Resumes MCCLK output and read data
6
0
R
-
has been halted during the command sequence.
CONTI
R/W
RD_
5
0
DATAEN
R/W
reception.
4
0
R
3
0
-
2
0
R
-
R
0
1
-
R
0
0
-