D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 548

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Interrupt Source
DMTE0
DMTE1
DMTE2
DMTE3
DMTE4
DMTE5
DMTE6
DMTE7
DMAE
DMABRGI0
DMABRGI1
DMABRGI2
Note: When DMA transfer ends while DMAOR.AE = 1 or DMAOR.NMIF = 1, requests may be
11.4.7
When the number of transfers specified in DMATCR has been finished and the IE bit in CHCR is
set to 1, a transfer-end interrupt request can be sent to the CPU from each channel. Table 11.10
lists the interrupt-request codes that are associated with these DMAC interrupts.
Table 11.10 DMAC Interrupt-Request Codes
Note: * A CH0 transfer-end interrupt cannot be generated when the DMABRG in DMABRG mode
Rev. 2.00 Feb. 12, 2010 Page 464 of 1330
REJ09B0554-0200
3. Set the channel resources corresponding to DMARSRA, DMARSRB to H'7F. (Write
4. Specify external address space in the corresponding channel SARn (the lower 6 bits are 32-
5. Specify H'0000 0001 in DMATCRn of the corresponding channel.
6. Specify CHCRn.DM [1:0] and SM [1:0] = 00 in the corresponding channel, and
7. Setting CHCRn.TE = 0 for the corresponding channel carries out DMA transfer for
8. Confirm that the corresponding channel DMARCR.REXn = 0.
H'FF.)
bit boundary), and P4 address H'FE09 0020 in DARn.
CHCRn.RS [3:0] = 0111.
requests that were retained in DMAC.
cleared even if DMARCR.REXn = 1. In that case, see “1. End of transfer with
DMAOR.AE = 1” and “2. End of transfer with DMAOR.NMIF = 1” in (2) Conditions for
Ending Transfer Simultaneously on All Channels of this section.
is used.
Interrupt-Request Codes
Description
CH0 transfer-end interrupt*
CH1 transfer-end interrupt
CH2 transfer-end interrupt
CH3 transfer-end interrupt
CH4 transfer-end interrupt
CH5 transfer-end interrupt
CH6 transfer-end interrupt
CH7 transfer-end interrupt
Address error interrupt
USB address error interrupt
All data transfer end interrupt
Half data transfer end interrupt
INTEVT Code
H'640
H'660
H'680
H'6A0
H'780
H'7A0
H'7C0
H'7E0
H'6C0
H'A80
H'AA0
H'AC0
Priority
High
Low