D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 634

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.3.1
CMTCFG is a 32-bit readable/writable register. The possible operations for a pin are timer
compare, timer input capture, up or down count, and capture input, where one pin is used for
capture while the second is used to enable the count.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 550 of 1330
REJ09B0554-0200
Bit
31 to 18 —
17
16
R/W:
R/W:
Bit:
Bit:
Configuration Register (CMTCFG)
Bit Name
ROT2
ROT0
R/W
31
15
R
0
-
-
ED3
R/W
30
14
-
-
R
0
R/W
29
13
R
0
-
-
Initial
Value
—
0
0
ED2
R/W
28
12
R
0
-
-
R/W
27
11
R
0
-
-
R/W
R
R/W
R/W
ED1
R/W
26
10
R
0
-
-
R/W
25
R
0
-
-
9
Description
Reserved
These bits can only be read from. The write value
should always be 0.
Channel 2, 3 Rotation Enable
Only set to 1 when operating in updown-counter
mode (T01=11, T23=011), otherwise this bit is
disabled (ROT2=0).
When this bit is set to 1, this indicates that pins of
channels 2 and 3 are operating in rotary mode. This
is an encoding of CMT_CTR2 pin and CMT_CTR3
pin to generate up and down signals to the counter.
Counter 3 needs to be disabled by clearing to 0 the
TE3 bit in CMTCTL.
Channel 0,1 Rotation Enable
Only set to 1 when operating in updown-counter
mode (T01=11, T23=011), otherwise this bit is
disabled (ROT0=0).
When this bit is set to 1, this indicates that pins of
channels 0 and 1 are operating in rotary mode. This
is an encoding of CMT_CTR0 pin and CMT_CTR1
pin to generate up and down signals to the counter.
Counter 1 needs to be disabled by clearing to 0 the
TE1 bit in CMTCTL.
ED0
R/W
24
R
0
8
-
-
23
R
R
7
0
-
-
-
FRCM FRTM
R/W
22
R
0
6
-
-
R/W
21
0
R
5
-
-
R/W
20
R
0
4
-
-
T23
R/W
19
0
R
3
-
-
R/W
18
0
R
2
-
-
ROT2
R/W
R/W
17
0
0
1
T01
ROT0
R/W
R/W
16
0
0
0