D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 921

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.16 Timer Control Register (CANTCR)
CANTCR is a 16-bit read/write register and provides functions to control the operation of the
Timer.
Initial value:
Bit
15
14
13
12
R/W:
Bit:
TCR15
Bit Name
TCR15
—
TCR13
TCR12
R/W
15
0
14
R
0
-
TCR13 TCR12 TCR11
R/W
13
0
Initial Value
0
0
0
0
R/W
12
0
R/W
11
0
R/W
R/W
—
R/W
R/W
10
R
0
-
R
9
0
-
Description
Enable Timer
When this bit is set, the timer is running. When
this bit is cleared the timer completes the current
cycle (notified by Timer overrun or a compare
match on CANTCMR) and is cleared to 0.
0: Timer stops running and is cleared at the end
1: Timer is running.
Reserved
The write value should always be 0. The read
value is not guaranteed.
TimeStamp Control for Reception
Specifies if the Timestamp in the message control
of each Mailbox is recorded at the StartOfFrame
(SOF) or EndOfFrame (EOF).
0: Timestamp is recorded at the SOF of every
1: Timestamp is recorded at the EOF of every
TimeStamp Control for Transmission
Specifies if the Timestamp of each transmit
Mailbox is recorded at the point that the
corresponding CANTXPR bit is set or the
corresponding CANTXACK is set when a
transmission request is made.
0: Timestamp is recorded at the point that the
1: Timestamp is recorded at the point that the
R
0
8
-
of the current cycle.
message received.
message received.
CANTXPR bit is set for message transmission.
CANTXACK bit is set for message
transmission.
R
7
0
-
Rev. 2.00 Feb. 12, 2010 Page 837 of 1330
R
0
6
-
TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0554-0200
R/W
0
2
R/W
1
0
R/W
0
0