D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 246

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3.3
In order to give priority to data reads to the cache and improve performance, this LSI has a write-
back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache
entry into external memory as the result of a cache miss. The write-back buffer contains one cache
line of data and the physical address of the purge destination.
7.3.4
This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or
writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as
the write to the write-through buffer is completed, without waiting for completion of the write to
external memory.
7.3.5
Setting the ORA bit in CCR to 1 enables half of the operand cache to be used as RAM. In cache
direct mapping mode, the 8-Kbyte area otherwise used for OC entries 256 to 511 is designated as a
RAM area. In double-size cache mode, a total of 16 Kbytes, comprising entries 256 to 511 in both
of the ways of the operand cache, is designated as a RAM area. Other entries can still be used as
cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-,
longword-, and quadword-size data reads and writes can be performed in the operand cache RAM
area. Instruction fetches cannot be performed in this area. This LSI cannot be used in OC index
mode when RAM mode is selected.
Examples of RAM usage is shown below.
• In cache direct mapping mode (EMODE = 0 in CCR)
Rev. 2.00 Feb. 12, 2010 Page 162 of 1330
REJ09B0554-0200
H'7C00 0000 to H'7C00 1FFF (8 Kbytes): RAM area (entries 256 to 511)
H'7C00 2000 to H'7C00 3FFF (8 Kbytes): RAM area (entries 256 to 511)
In the same pattern, shadows of the RAM area are created in 8-Kbyte blocks until H'7FFF
FFFF is reached.
Write-Back Buffer
Write-Through Buffer
RAM Mode
:
Physical address bits [28:5]
Figure 7.4 Configuration of Write-Through Buffer
Figure 7.3 Configuration of Write-Back Buffer
:
Physical address bits [28:0]
LW0
LW1
LW2
LW3
LW0
:
LW1
LW4
LW5
LW6
LW7