D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 402

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.14 shows the SRAM write timing when DCKDR is set to 1/2.
The negate timing for CS1 and RD should be set as follows:
10.6.4
(1) Synchronous DRAM Connection System
Since synchronous DRAM is selectable with the CS signal, it can be connected to off-chip
memory space areas 2 and 3 and share usage of RAS and other control signals. If bits DRAMTP2
to DRAMTP0 in BCR1 are 010, area 3 becomes a synchronous DRAM interface. If set to 011,
areas 2 and 3 both become synchronous DRAM interfaces.
This LSI supports burst read and burst write modes with a burst length of 4 as a synchronous
DRAM operating mode. The data bus width is 32 bits, and the SZ bits in MCR must be set to 11.
Rev. 2.00 Feb. 12, 2010 Page 318 of 1330
REJ09B0554-0200
Number of Inserted Wait
Cycles during Data Holding
D31 − D0
A25 − A0
RD/WR
(write)
CKIO
WEn
DCK
CS1
BS2
BS
Figure 10.14 DCK, BS2, and CS1 Timing when Writing to SRAM Interface
Synchronous DRAM Interface
0
1
2
3
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles)
TS1
T1
Tw
0
0
1
1
A1H[1:0]
Tw
Tw
T2
0
1
0
1
TH1
TH2
0
0
1
1
CSH[1:0]
0
1
0
1