D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 185

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(e) Flow dependency
MOV
ADD
FADD
FLOAT
FMOV.S FR0,@-R15
MOV.L @R1,R1
SHAD
next
FADD
STS
STS
ADD
MOV.L @R1,R1
next
MOV.L @R1,R1
ADD
next
FLDI1
FIPR
FMOV
FTRV
FMOV
FMOV
R0,R1
R2,R1
DR0,DR2
R1,R2
FR1,FR2
FPUL,R1
FPSCR,R2
R2,R1
R0,R1
FR3
FV0,FV4
@R1,XD14
XMTRX,FV0
FR3,FR5
FR2,FR4
FPUL,DR0
Figure 5.3 Examples of Pipelined Execution (cont)
1 stall cycle
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
D
D
I
I
D
I
I
I
I
I
D
D
i
Zero-cycle latency
Zero-cycle latency
1-cycle latency
...
...
...
F1
EX
EX
EX
EX
EX
F1
F1
EX
EX
D
D
D
D
d
d
I
3 stall cycles
2 stall cycles
1 stall cycle
2 stall cycles
EX
F2
F1
NA
NA
NA
EX
MA
MA
F2
F1
F2
NA
MA
d
2-cycle latency
2-cycle latency
2-cycle latency
NA
FS
F1
FS
F2
MA
EX
FS
F2
S
S
S
S
S
d
d
S
d
S
d
4-cycle latency for FPSCR
3-cycle latency for upper/lower FR
3-cycle increase
3 stall cycles
1-cycle increase
FR1 write
1-cycle increase
EX
FS
F2
FS
EX
NA
F1
F0
F0
S
d
d
S
D
FR0 write
EX
NA
FS
F1
MA
F0
F2
F1
F1
d
S
Rev. 2.00 Feb. 12, 2010 Page 101 of 1330
FS
NA
F2
F2
F1
F1
F2
F0
S
S
d
The following instruction, ADD, is not
stalled when executed after an instruction
with zero-cycle latency, even if there is
dependency.
ADD and MOV.L are not executed in
parallel, since MOV.L references the result
of ADD as its load address.
Because MOV.L and ADD are not fetched
simultaneously in this example, ADD is
stalled for only 1 cycle even though the
latency of MOV.L is 2 cycles.
Due to the flow dependency between the
load and the SHAD/SHLD shift amount,
the latency of the load is increased to 3
cycles.
FS
F2
FS
S
FS
F2
F1
F0
D
FR3 write
7-cycle latency for lower FR
FS
EX
FS
F2
F1
D
FR2 write
8-cycle latency for upper FR
FS
NA
EX
F2
FS
NA
REJ09B0554-0200
S
S