D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 693

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
Figure 17.10 shows an example of the operation for transmission in asynchronous mode.
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-
data-empty interrupt (TXI) request is generated.
The serial transmit data is sent from the SCIF_TXD pin in the following order.
A. Start bit: One 0-bit is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. A format in which a parity bit is
D. Stop bit(s): One or two 1-bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If there is no transmit data after the stop bit is sent, the TEND flag in SCFSR is set to 1, the
stop bit is sent, and then the line goes to the mark state in which 1 is output from the
SCIF_TXD pin.
Serial
data
TDFE
TEND
1
TXI interrupt
request
Start
bit
not output can also be selected.
0
sent.
Figure 17.10 Sample SCIF Transmission Operation
Data written to SCFTDR
and TDFE flag read as 1
then cleared to 0 by TXI
interrupt handler
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
One frame
Data
D7
Parity
bit
0/1
TXI interrupt
request
Stop
bit
1
Start
bit
0
D0
D1
Rev. 2.00 Feb. 12, 2010 Page 609 of 1330
Data
D7
Parity
bit
0/1
Stop
bit
1
Idle state
(mark state)
REJ09B0554-0200
1