UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 131

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address
F01AAH
F01ABH
F01ACH
F01ADH
F01AEH
F01BAH
F01BBH
F01BCH
F01BDH
F01BEH
F01A0H
F01A1H
F01A2H
F01A3H
F01A4H
F01A5H
F01A6H
F01A7H
F01A8H
F01A9H
F01AFH
F01B0H
F01B1H
F01B2H
F01B3H
F01B4H
F01B5H
F01B6H
F01B7H
F01B8H
F01B9H
F01BFH
F01C0H
F01C1H
F01C2H
F01C3H
F01C4H
F01C5H
Timer status register 00
Timer status register 01
Timer status register 02
Timer status register 03
Timer status register 04
Timer status register 05
Timer status register 06
Timer status register 07
Timer channel enable status
register 0
Timer channel start trigger register
0
Timer channel stop trigger register
0
Timer clock select register 0
Timer channel output register 0
Timer channel output enable
register 0
Timer channel output level register
0
Timer channel output mode register
0
Timer counter register 08
Timer counter register 09
Timer counter register 10
Special Function Register (SFR)
Name
Table 3-6. Extended SFR (2nd SFR) List (4/6)
TSR00
TSR01
TSR02
TSR03
TSR04
TSR05
TSR06
TSR07
TE0
TS0
TT0
TPS0
TO0
TOE0
TOL0
TOM0
TCR08
TCR09
TCR10
CHAPTER 3 CPU ARCHITECTURE
Symbol
User’s Manual U19678EJ1V1UD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
16-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Reset
After
√
√
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√
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√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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√
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√
√
√
√
√
√
√
√
√
√
√
√
√
129
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√