UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 597

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Scan mode
A/D conversion
The four analog input channels of scans 0 to 3, which are specified by the analog input channel specification
register (ADS), while the ADMD bit of A/D converter mode register (ADM) is 1, are A/D converted successively.
A/D conversion is performed in sequence, starting from the analog input channel specified by scan 0.
When A/D conversion of one analog input is complete, the conversion result is stored in the A/D conversion result
register (ADCR) and the A/D conversion end interrupt request signal (INTAD) is generated.
The A/D conversion results of all the analog input channels are stored in ADCR. It is therefore recommended to
save the contents of ADCR to RAM, once A/D conversion of one analog input channel has been completed.
When one A/D conversion ends, the next A/D conversion is started successively, regardless of being set to the
trigger mode.
If anything is written to ADM, ADM1, or ADS during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the analog input channel of scan 0, regardless of being in the software trigger
mode or timer trigger mode (hardware trigger mode).
operation
ADCRH
ADCR,
INTAD
ANI0
ANI1
ANI2
ANI3
Conversion start
Set ADCS bit = 1
Data 1
Data 1
(ANI0)
Figure 12-16. Example of Scan Mode Operation Timing
Data 1
(ANI0)
Data 2
Data 2
(ANI1)
Data 2
(ANI1)
CHAPTER 12 A/D CONVERTER
Data 3
Data 3
(ANI2)
User’s Manual U19678EJ1V1UD
Data 3
(ANI2)
Data 4
Data 4
(ANI3)
Data 4
(ANI3)
Data 5
Data 5
(ANI0)
Data 5
(ANI0)
Data 6
Data 6
(ANI1)
Data 6
(ANI1)
Data 7
Data 7
(ANI2)
Data 7
(ANI2)
Conversion stop
Set ADCS bit = 0
Data 8
Data 8
(ANI3)
Data 8
(ANI3)
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